As is known in the art, monolithic microwave integrated circuits (MMICs) are used extensively in a wide variety of microwave circuit applications. These MMICs have a substrate with a semiconductor layer on the upper surface of the substrate. Active devices are formed with the semiconductor layer and passive devices and interconnecting transmission lines are disposed on the upper surface to form the microwave circuit. In some circuit applications it is necessary include a power dissipating, resistive load.
More particularly, in a radar system, as shown in FIG. 1A, a transmitter section sends radar pulses to an antenna through a circulator, or duplexer and radar return signals are directed by the circulator to a receiver section through a power limiter/load section and low noise amplifier (LNA), as shown. The power limiter/load section is often required to protect the sensitive low noise amplifier (LNA) from permanent degradation or catastrophic failure due to high incident signal levels appearing at the antenna element. Without a limiter, the LNA can usually tolerate signal levels well beyond its input 1 dB gain compression point (P1dB). The gain of the LNA will decrease further beyond the 1 dB point with increasing input levels as its multiple gain stages are forced into saturation. At some point, the input level will be sufficient to induce permanent degradation from excessive voltage breakdown or power dissipation in the 1st stage transistor gate structure depending on the DC biasing approach and other design factors. For a GaAs pHEMT LNA, the damaging power level for a continuous wave (CW) input signal is typically in the range of 0.2-2 W depending on the design while GaN HEMT LNAs survive well above those input power levels. Since most receiver systems are susceptible to input power levels at the antenna well above the pHEMT LNA's damage level, a power sensitive, self-actuating attenuator circuit known as a power limiter/load section is installed ahead of the LNA to reduce incident levels at the LNA input below the damage threshold
The schematic of one power limiter/load section is shown in more detail in FIG. 1B. It is noted that the power limiter/load section has a power level sensing circuit and a power dissipating load. In normal operation, a voltage VLIN is applied to the gates of FET 1 and FET 2 to place the FETs in a non-conducting condition. In such condition, an input microwave signals from a circulator in the radar system of FIG. 1A is fed to the power level sensing circuit. If the power in the input microwave signal is below a predetermined level, set by the power level sensing circuit, the input microwave signal passes to the LNA (FIG. 1A) through a quarter wave transmission line. If, on the other hand, the power level of the input microwave signal exceeds the predetermined power level, the power level sensing circuit produces a signal on the gates of both FET 1 and FET 2 placing both FET 1 and FET 2 in a conducting condition, the output side of the quarter wave transmission line is thereby connected to ground so that the short circuit impedance is transformed to an open circuit at the input side of the quarter wave transmission line therefore blocking the input microwave signal from passing to the LNA and further the input microwave signal passes through the conducting mode FET 1 to the impedance matched resistive power dissipating load. It is noted that in some cases, as during transmit mode, it is desired to have any power entering the power limiter/load section pass to the resistive power dissipating load even if the level of the input signal is less the predetermined power level. In this case, a signal VLIM is fed to the gates of both FET 1 and FET 2 placing them both in a conducting condition with the result that the microwave signal at the input to the circuit is fed to the resistive power dissipating load.
In some applications requiring high levels of power dissipation, a resistive load, such as Tantalum Nitride (TaN), is used. However, because, inter alia, of their relatively large size which would occupy a large portion of a MMIC substrate, two different substrates are used for the power limiter/load section as shown in FIGS. 1B and 1C; one substrate is a heat spreading substrate, such as a beryllium oxide (BeO) substrate, with power dissipating load on upper surface, such as TaN and a second substrate, such as a silicon carbide (SiC) substrate is used for the MMIC where a Group III-V layer, such as GaN on the upper surface of the SiC substrate is used for forming active devices, such as Field Effect Transistors (FETs) interconnected to passive devices with microwave transmission lines arranged as the power level sensing circuit. It is noted that the in this example, the resistive loads, here three resistors, R1, R2 and R3 are disposed on the upper surface of the heat spreading substrate, BeO. As is also known in the art, the microwave transmission lines typically have a ground plane conductor on the bottom surface of the substrates, as for example in a microwave transmission line of a coplanar waveguide (CPW) transmission line where electrically conductive vias are used to connect the ground plane conductors of the CPW to a ground plane conductor on the back surface of the substrate, as shown for the BeO substrate in FIG. 1D. Unfortunately, because of the large surface area of the resistor, a parasitic capacitance is created between the resistor, the underlying portion of the ground plane conductor, and the BeO there between. In order to compensate for this capacitance and provide a matched impedance to the transmission line, additional capacitors C1, C2 and inductors L1-L4 are arranged to provide an impedance matching network for the high power load section, as shown in FIG. 1E.